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1/15 ? semiconductor msm518128/l description the msm518128/l is a 131,072-word 8-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm518128/l achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm518128/l is available in a 26/24-pin plastic soj. the msm518128l (the low-power version) is specially designed for lower-power applications. features ? 131,072-word 8-bit configuration ? single 5 v power supply, 5% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 512 cycles/8 ms, 512 cycles/64 ms (l-version) ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package: 26/24-pin 300 mil plastic soj (soj26/24-p-300-1.27) (product : msm518128/l-xxjs) xx indicates speed rank. product family ? semiconductor msm518128/l 131,072-word 8-bit dynamic ram : fast page mode type msm518128/l-50 50 ns 100 ns 120 ns 630 mw 525 mw 5.25 mw/ family access time (max.) cycle time (min.) standby (max.) power dissipation msm518128/l-60 t rac 60 ns 26 ns t aa 30 ns 14 ns t cac 15 ns 14 ns t oea 15 ns msm518128/l-45 45 ns 90 ns 682.5 mw 24 ns 13 ns 13 ns operating (max.) 1.05 mw (l-version) e2g0012-17-41 this version: jan. 1998 previous version: may 1997
2/15 ? semiconductor msm518128/l pin configuration (top view) 3 4 5 9 10 11 12 13 dq2 dq3 dq4 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 dq7 dq6 dq5 a8r a7 a6 a5 a4 2 dq1 25 dq8 1 v ss 26 v ss 26/24-pin plastic soj 6 we 21 cas 8 ras 19 oe pin name function a0 - a7, a8r address input ras row address strobe cas column address strobe dq1 - dq8 data input/data output oe output enable we write enable v cc power supply (5 v) v ss ground (0 v) note: the same gnd voltage level must be provided to every v ss pin.
3/15 ? semiconductor msm518128/l block diagram timing generator ras cas timing generator internal address counter row address buffers v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 8 dq1 - dq8 8 8 8 8 8 input buffers 8 8 a0 - a7 9 8 8 1 a8r column address buffers
4/15 ? semiconductor msm518128/l electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.75 0 2.4 C1.0 min. 5.25 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a7, a8r) input capacitance ( ras , cas , we , oe ) output capacitance (dq1 - dq8) c in1 symbol c in2 c i/o 6 7 7 max. pf unit pf pf parameter (v cc = 5 v 5%, ta = 25c, f = 1 mhz) typ.
5/15 ? semiconductor msm518128/l dc characteristics parameter symbol condition msm518128 /l-45 msm518128 /l-50 msm518128 /l-60 (v cc = 5 v 5%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.25 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t pc = min. (fast page mode) t rc = 125 m s, average power v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 i cc10 cas before ras , supply current t ras 1 m s (battery backup) 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 130 2 1 130 5 130 100 300 200 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 120 2 1 120 5 120 90 300 200 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 100 2 1 100 5 100 80 300 200 unit v v m a m a ma ma ma ma ma ma m a m a note 1, 2 1 1, 2 1 1, 2 1, 3 1, 4, 5 1, 5 ras cycling, notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/15 ? semiconductor msm518128/l ac characteristics (1/2) parameter random read or write cycle time (v cc = 5 v 5%, ta = 0c to 70c, input pulse levels 0 v to 3 v) note 1, 2, 3 read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from oe output low impedance time from cas transition time refresh period refresh period (l-version) ras precharge time ras pulse width (fast page mode) ras hold time cas precharge time (fast page mode) cas pulse width ras pulse width cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from cas precharge oe to data output buffer turn-off delay time ras hold time referenced to oe note 4, 5, 6 4, 5 4, 6 4 7 3 5 6 4 7 4 ras hold time from cas precharge cas to data output buffer turn-off delay time symbol t rc t rwc t pc t prwc t rac t cac t aa t oea t clz t off t t t ref t ref t rp t ras t rasp t rsh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t cpa t oez t roh t rhcp min. 90 140 34 75 0 0 3 35 45 45 14 10 14 45 5 17 12 0 7 0 12 35 20 0 10 28 max. 45 14 24 14 10 50 8 64 10,000 100,000 10,000 31 21 28 10 unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 100 150 36 77 0 0 3 40 50 50 14 10 14 50 5 18 13 0 8 0 13 40 26 0 10 30 max. 50 14 26 14 10 50 8 64 10,000 100,000 10,000 36 24 30 10 max. 60 15 30 15 10 50 8 64 10,000 100,000 10,000 45 30 35 10 min. 120 170 40 90 0 0 3 50 60 60 15 10 15 60 5 20 15 0 10 0 15 50 30 0 10 35 msm518128 /l-45 msm518128 /l-50 msm518128 /l-60 read command set-up time t rcs read command hold time t rch read command hold time referenced to ras t rrh ns ns ns 0 0 0 0 0 0 0 0 0 8 8
7/15 ? semiconductor msm518128/l ac characteristics (2/2) symbol parameter write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cas lead time data-in set-up time t wcs t wch t wcr t wp t rwl t cwl t ds data-in hold time t dh data-in hold time from ras t dhr cas to we delay time t cwd column address to we delay time t awd ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) t rwd t rpc t csr t chr oe command hold time t oeh oe to data-in delay time t oed cas precharge we delay time t cpwd unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 0 12 35 10 14 14 0 12 35 36 48 70 0 10 25 12 12 50 max. min. 0 13 40 10 14 14 0 13 40 38 52 75 0 10 25 13 13 53 max. min. 0 15 50 10 15 15 0 15 50 50 60 85 0 10 30 15 15 60 max. note 9 9 9 9 9 10 10 (v cc = 5 v 5%, ta = 0c to 70c, input pulse levels 0 v to 3 v) note 1, 2, 3 msm518128 /l-45 msm518128 /l-50 msm518128 /l-60
8/15 ? semiconductor msm518128/l notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 50 pf. the output timing reference levels are v oh = 2.0 v and v ol = 0.8 v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
9/15 ? semiconductor msm518128/l timing waveform read cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t cwl t rwl "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t off open t clz valid data-out write cycle (early write) e2g0092-17-41e
10/15 ? semiconductor msm518128/l "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh read modify write cycle
11/15 ? semiconductor msm518128/l fast page mode read cycle fast page mode write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v il C C we v ih v il C C t rasp t rp t ar t crp t rcd t cas t cp t cas t rsh t crp t cas t asr t rah t cah t csh t asc t cah t asc t cah t ral row column column column t rad t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in t dhr note: oe = "h" or "l" v ih t asc t pc t rhcp t cp t cwl t cwl t rwl t cwl t wcr "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rasp t rp t ar t crp t rcd t pc t rsh t crp t cas t cas t cp t cas t rad t asr t rah t asc t cah t csh t asc t cah t asc t cah t ral row column column column t rcs t rch t rcs t rcs t rch t aa t oea t aa t aa t rrh t oea t oea t cac t rac t off t oez t cac t clz t off t oez t cac t clz t oez t off t clz valid data-out valid data-out valid data-out t rhcp t cp t rch t cpa t cpa
12/15 ? semiconductor msm518128/l ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" open t off fast page mode read modify write cycle t wp ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C we v ih v il C C dq v i/oh v i/ol C C t rasp t ar t rp t csh t prwc t rsh t rcd t cas t cp t cas t cp t cas t crp t rad t rah t asr t asc t cah t asc t cah t asc t cah t ral row column column column t rwd t rcs t cwd t cwl t cwd t cwl t cwd t rwl t cwl t awd t awd t awd t oea t wp t oea t wp t oea t aa t oed t cac t ds t dh t cac t aa t rac t ds t dh t cpa t oed t cac t aa t ds t dh t clz t clz t clz out in out out in in t roh t oez t oez t cpa t oed t rcs t rcs t cpwd t cpwd "h" or "l" t oez ras -only refresh cycle
13/15 ? semiconductor msm518128/l ras cas v ih v il C C v ih v il C C column row dq v oh v ol C C we v ih v il C C oe v ih v il C C address v ih v il C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t asc t rah t cah t rcs t ral t rrh t aa t roh t oea t cac t clz t rac t off t oez valid data-out "h" or "l" cas before ras refresh cycle hidden refresh read cycle ras cas v ih v il C C v ih v il C C t chr note: we , oe , address = "h" or "l" dq v oh v ol C C t rc t rp t ras t rp t rpc t cp t csr t rpc t off open "h" or "l"
14/15 ? semiconductor msm518128/l hidden refresh write cycle ras cas v ih v il C C v ih v il C C dq v ih v il C C we v ih v il C C oe v ih v il C C address v ih v il C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asc t asr t rah t cah t ral row column t wcs t wch t wp t ds t dh valid data-in t dhr "h" or "l" t wcr
15/15 ? semiconductor msm518128/l notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit : mm) package dimensions soj26/24-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish

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